module frequency_10Hz(
	input clk_51200Hz,
	input rst_n,
	output reg clk_10Hz  //51200 / 10 = 5120; 5120 / 2 - 1 = 2559
);

	reg[11:0] count;
	
	always @(posedge clk_51200Hz or negedge rst_n) begin
		if(rst_n == 1'b0) begin
			count = 12'd0;
			clk_10Hz = 1'b0;
		end
		else begin
			if(count == 12'd2559) begin
				count = 12'd0;
				clk_10Hz = ~clk_10Hz;
			end
			else begin
				count = count + 12'd1;
			end
		end
	end

endmodule
